The present invention relates to the gate etching process used during integrated circuit fabrication. More specifically, the present invention pertains to a method to make the gate etching endpoint signal stronger and more consistent.
Integrated circuits are fabricated en masse on silicon wafers using well-known techniques such as photolithography. Using these techniques, a pattern (xe2x80x9cmaskxe2x80x9d) that defines the size and shape of the components and gates within a given layer of the die is applied to the wafer. The pattern applied to the wafer is laid out in an array, or matrix, of reticle images. A wafer stepper holds the pattern over a wafer and projects the pattern image of the reticle onto the wafer.
Prior Art FIG. 1A shows a laminate 10 used in the fabrication of integrated circuits in accordance with one typical prior art embodiment. Laminate 10 includes a substrate 15 (e.g., a silicon-based semiconductor), a gate dielectric layer 16 (e.g., silicon dioxide or some other dielectric material), and a gate electrode layer 17 (e.g., n-doped polysilicon).
With reference next to Prior Art FIG. 1B, in order to form gate 20, portions of gate electrode layer 17 are removed, typically using a gate etch process. As described above, a photolithography process is used in a known manner to apply a gate mask 22 at the location at which gate 20 will be formed. When an etchant (e.g., a plasma etch) is then applied, the portions of gate electrode layer 17 around gate 20 are removed, while the material under gate mask 22 remains to form the gate (see Prior Art FIG. 1C).
Traditionally, integrated circuits were made with n-type polysilicon gates. The polysilicon was doped n-type during polysilicon deposition by adding PH3 or after polysilicon deposition using POCl3. Thus, the gate etch process had to remove only n-type polysilicon in order to form the gates.
For deep submicron CMOS (complementary metal-oxide semiconductor) circuits, dual-implanted polysilicon or amorphous silicon is preferred (for simplicity in the discussion, both will be referred to as xe2x80x9cpolysiliconxe2x80x9d or xe2x80x9cpolyxe2x80x9d). After depositing undoped poly, implant masks are used to create n-type poly over n-channel transistors and p-type poly over p-channel transistors. Depending on the implant mask arrangement, some portions of the poly may not be doped at all (xe2x80x9cundopedxe2x80x9d or xe2x80x9cunimplantedxe2x80x9d), and other portions may be doped with both types of dopant material (n/p-doped). Such dual-implanted polysilicon allows for better control of the p-channel transistor properties.
However, the dual-implanted poly can create a problem during the gate etch process, because some combination of undoped, n-doped, p-doped, and n/p-doped poly will be exposed to the etchant. Each of these differently doped polysilicons will etch at a different rate. In general, p-doping will depress the etch rate, while n-doping will enhance it. The difference in etch rates can be significant; for example, when HBr/O2 etchant is used, the difference in the etching rate between p-doped poly and n-doped poly can be as much as 37 percent. Such large differences in etch rates increase the likelihood of microtrenching of the gate oxide layer; that is, a local breakthrough of the gate oxide layer followed by etching into the silicon layer adjacent to the gate oxide layer. Microtrenching is not desirable because it introduces a variable into the fabrication process and may also affect the electrical properties of the integrated circuit.
Prior Art FIG. 2A shows a laminate 30 used in the fabrication of integrated circuits (e.g., a CMOS) in accordance with one typical prior art embodiment. Laminate 30 includes a substrate 35, typically a silicon-based semiconductor layer; a gate dielectric layer 36, typically silicon dioxide or some other dielectric material; and gate electrode layer 37, typically doped polysilicon. Here, a p-gate 41 and an n-gate 42 are to be formed in the particular locations shown. Accordingly, gate electrode layer 37 includes a p-doped region 43 encompassing the location of p-gate 41 and an n-doped region 44 encompassing the location of n-gate 42.
In the prior art, the p-dopant material and the n-dopant material are implanted in a known manner using implant masks. These implant masks are used to broadly implant the correct dopant material in the proper locations (e.g., p-doped region 43 and n-doped region 44). P-gate 41 and n-gate 42 are then formed by removing the excess portions of gate electrode layer 37 using a gate etch process. Since the excess portions are removed to form the gate, in general it is important only that the doped regions bound the locations where the gates will be formed.
With reference now to Prior Art FIG. 2B, p-doped region 43 will etch away at a slower rate than n-doped region 44. As a result, when n-doped region 44 has been removed by etching, forming n-gate 42, portions of the p-doped region (p-doped regions 43a and 43b) will still remain. Should the gate etch process continue in order to remove p-doped regions 43a and 43b, the etchant can form microtrenches (e.g., microtrench 50) in gate dielectric layer 35.
To avoid microtrenching while retaining the benefits of dual-implanted poly in CMOS design, it is important to signal endpoint when n-doped region 44 is cleared. At endpoint, the gate etch process is halted, and a different etchant is introduced. The new etchant exhibits greater selectivity between p-doped regions 43a and 43b and gate dielectric layer 35; that is, the new etchant will work to clear p-doped regions 43a and 43b without operating on gate dielectric layer 35, so that microtrenches will not be formed.
However, a problem in the prior art is that the endpoint signal may be too weak to detect; therefore, it does not trigger endpoint and the switch to the different etchant. In those cases, the gate etch process continues for too long using the nonselective etchant, and microtrenching is thus likely to occur.
Accordingly, what is needed is a method and/or apparatus that can improve the endpoint signal, so that endpoint is consistently triggered at the correct moment and microtrenching is prevented. What is also needed is a method and/or apparatus that can address the above need and that can be used with laminates using various combinations of undoped, n-doped, p-doped, and n/p-doped polysilicon with significantly different etch rates. The present invention provides a novel solution to the above needs.
These and other objects and advantages of the present invention will become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
The present invention provides a method and apparatus thereof that can improve the endpoint signal, so that endpoint is consistently triggered at the correct moment and microtrenching is prevented. The present invention can also be used with laminates using various combinations of undoped, n-doped, p-doped, and n/p-doped polysilicon with significantly different etch rates.
In accordance with the present embodiment of the present invention, detection of the gate etch endpoint signal is improved by maximizing the use of a faster etching dopant material and minimizing the use of a slower etching dopant material in the gate electrode layer. The faster etching dopant material will etch away faster, and because the gate electrode layer is predominantly made up of the faster etching dopant material, a strong and detectable endpoint signal will be induced when the etchant reaches the silicon dioxide layer.
In one embodiment, a first portion of the gate electrode layer, substantially corresponding only to the location at which a gate is to be formed, is doped with the slower etching dopant material. A second portion of the gate electrode layer, larger than the first portion, is doped with the faster etching dopant material. Alternatively, the remaining portion of the gate electrode layer (that portion not doped with the slower etching dopant material) is doped with the faster etching dopant material. In either case, more of the gate electrode layer is doped with the faster etching dopant material than with the slower etching dopant material. A gate mask is aligned over the gate electrode layer, and the unmasked portions of the gate electrode layer are removed using an etchant. Because the gate electrode layer is predominantly made up of the faster etching dopant material, a strong and detectable endpoint signal will be induced when the etchant reaches the silicon dioxide layer, as described above.
In another embodiment of the present invention, an implant mask is aligned over the gate electrode layer within an alignment tolerance. The implant mask allows a first dopant material to be implanted into the gate electrode layer at a location where a gate is to be formed. In one embodiment, the implant mask is sized so that the first dopant material does not extend beyond the edges of the gate including the alignment tolerance. In another embodiment, the implant mask is sized so that the first dopant material does not extend beyond the edges of the gate (with no allowance for alignment tolerance). In still another embodiment, the implant mask is sized so that the first dopant material does not extend to the edges of the gate. Similarly, a second implant mask is used to implant a second dopant material into the gate electrode layer at a location where a second gate is to be formed. In its various embodiments, the second implant mask is also sized so that the second dopant material does not extend beyond the edges of the second gate including the alignment tolerance, does not extend beyond the edges of the second gate (with no allowance for alignment tolerance), or does not extend to the edges of the gate. In these embodiments, a gate mask is aligned over the dopant material(s), and the unimplanted gate electrode layer not under the gate mask is removed using an etchant. Because the gate etch will see only the unimplanted portions of the gate electrode layer, all portions will signal the endpoint at about the same time, and so a strong and consistent endpoint signal can be detected.
Alternatively, the second dopant material can be implanted into the portion of the gate electrode layer not implanted with the first dopant material. As described above, in this embodiment the gate electrode layer is predominantly made up of the faster etching dopant material, and so a strong and detectable endpoint signal will be induced when the etchant reaches the silicon dioxide layer.
In the present embodiment, the integrated circuit is a deep submicron complementary metal-oxide semiconductor (CMOS). In one embodiment, the laminate used to fabricate the integrated circuit and gates in accordance with the present invention is comprised of a silicon dioxide gate dielectric layer above a silicon-based semiconductor substrate. In one embodiment, the gate electrode layer is comprised of polysilicon, and in another embodiment the gate electrode layer is comprised of amorphous silicon.